50, 90 and 100 Ω trace width: stripline, 0.10 mm and 0.15 mm dielectric, Dk 4.5, 35 µm copper
Inner-layer trace between two solid planes: h1 = 0.10 mm below it, h2 = 0.15 mm from the trace base to the far plane, Dk 4.5 both sides, 35 µm (1 oz) copper.
Built by AI agents; confirm with your fab. These numbers are computed for the cross-section stated here, not for any fab's stackup. They are a starting point for a layout, not a guarantee of what your board will measure.
50 Ω single-ended
| Width, mm | Width, mil | Z, field solver | εeff | Formula | 3D FDTD |
|---|---|---|---|---|---|
| 0.059 ⚠ | 2.32 | 50.00 | 4.50 | 49.8 (-0.5%) | not run |
90 Ω differential
| Width, mm | Gap, mm | W / gap, mil | Zdiff, field solver | εeff odd | Formula | 3D FDTD |
|---|---|---|---|---|---|---|
| 0.043 ⚠ | 0.100 | 1.69 / 3.94 | 89.97 | 4.50 | 97.5 (+8.3%) | not run |
| 0.056 ⚠ | 0.130 | 2.20 / 5.12 | 89.88 | 4.50 | 93.4 (+4.0%) | not run |
| 0.061 ⚠ | 0.150 | 2.40 / 5.91 | 90.22 | 4.50 | 92.4 (+2.5%) | not run |
| 0.070 ⚠ | 0.200 | 2.76 / 7.87 | 90.12 | 4.50 | 90.7 (+0.6%) | not run |
| 0.075 ⚠ | 0.250 | 2.95 / 9.84 | 89.87 | 4.50 | 89.8 (-0.1%) | not run |
| 0.077 ⚠ | 0.300 | 3.03 / 11.81 | 90.00 | 4.50 | 89.6 (-0.4%) | not run |
| 0.079 ⚠ | 0.400 | 3.11 / 15.75 | 89.91 | 4.50 | 89.4 (-0.6%) | not run |
⚠ Every row here is finer than 0.10 mm in width or gap.
100 Ω differential
| Width, mm | Gap, mm | W / gap, mil | Zdiff, field solver | εeff odd | Formula | 3D FDTD |
|---|---|---|---|---|---|---|
| 0.042 ⚠ | 0.150 | 1.65 / 5.91 | 100.05 | 4.50 | 103.3 (+3.3%) | not run |
| 0.050 ⚠ | 0.200 | 1.97 / 7.87 | 100.18 | 4.50 | 101.2 (+1.0%) | not run |
| 0.054 ⚠ | 0.250 | 2.13 / 9.84 | 100.22 | 4.50 | 100.4 (+0.2%) | not run |
| 0.057 ⚠ | 0.300 | 2.24 / 11.81 | 99.73 | 4.50 | 99.6 (-0.2%) | not run |
| 0.058 ⚠ | 0.400 | 2.28 / 15.75 | 100.15 | 4.50 | 99.8 (-0.4%) | not run |
⚠ Every row here is finer than 0.10 mm in width or gap.
Nearby cross-sections
- stripline, 0.15 mm and 0.15 mm dielectric, Dk 4.5, 35 µm copper
- stripline, 0.10 mm and 0.10 mm dielectric, Dk 4.5, 35 µm copper
- stripline, 0.10 mm and 0.20 mm dielectric, Dk 4.5, 35 µm copper
- stripline, 0.10 mm and 0.15 mm dielectric, Dk 4.5, 18 µm copper
What these numbers assume
- A round grid, not your stackup: these tables step through round values of height, Dk and copper. They aren't any fab's build. Use the calculators for your fab's actual values.
- Reference planes: solid planes directly below an outer trace, and on both sides of an inner trace, with nothing cut out under the trace. Other references (skipping a layer, coplanar ground) change the answer and are not in these tables.
- Cross-section: rectangular trace, no etch taper, width as drawn, copper thickness as stated. Real etching makes the top narrower and raises impedance a little. Outer copper is usually plated up, so a finished outer layer is often thicker than its starting foil.
- Stripline position: the trace sits on the first dielectric, height h1. The second height, h2, runs from the bottom of the trace to the far plane, so it includes the copper. One Dk on both sides.
- Solder mask on outer layers: our round assumption, not a measurement: Dk 3.5, 25 µm on bare laminate, 15 µm on copper, 25 µm between a pair. Real mask varies, and it lowers impedance by a few percent, so ask your fab.
- Frequency: a quasi-static 2D solve, with no conductor loss, no roughness and no dispersion. Dk has no frequency correction. Expect the real line to differ at high frequency.
- Field solver column: the impedance of the exact width and gap printed in the row, solved again after rounding to 1 µm.
- Formula column: a closed form for the same width, shown for comparison only. Microstrip uses IPC-2141A, uncoated, with a differential factor as widely quoted. Stripline uses Wheeler's 1978 formula with the two sides in parallel. Their limits are narrow and they ignore the mask, so a difference there isn't an error in the solver. A microstrip row with w/h outside 0.1 to 2.0 says “outside its range”.
- 3D FDTD column: an openEMS run for that exact row where we ran it. “Not run” means no 3D solve exists for that row. Almost all rows are 2D-solved only: see how it was checked.
- ⚠ under 0.10 mm: a round line we chose to flag fine geometry, not any fab's rule. Your fab's minimum decides what can be built.
- Tolerance: Dk, prepreg flow, etching and plating all move a real board. Ask your fab for an impedance-controlled quote, and give them the target rather than these widths, since a fab will adjust width to hit it.
Sources: computed here. Closed forms from IPC-2141A (2004) and Wheeler (1978). Method on the how it was checked page.